1. Field of the Invention
Embodiments of the present invention relate to a semiconductor device having a single chip in which a memory device and a logic device are formed, and a method for manufacturing the semiconductor device. This application claims priority under 35 USC § 119 to Korean Patent Application No. 2003-57771, filed on Aug. 21, 2003, the contents of which are herein incorporated by reference in its entirety for all purposes.
2. Description of the Related Art
As a result of relatively high integration of semiconductor devices, there has been the development of a multi-chip structure having a memory device and a logic device formed in a single chip. The memory device may include a volatile memory device (e.g. a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device) or a non-volatile memory device (e.g. a flash memory device). When the memory device and the logic device are included in the single chip, the multi-chip may have relatively small size, relatively low consumption power, relatively rapid operation, and relatively low electro magnetic interference (EMI).
For example, a multi-chip may include a merged DRAM & logic (MDL) device (in which a DRAM device and a logic device are incorporated together), or a merged flash & logic (MFL) device (in which a flash memory device and a logic device are incorporated together).
A gate electrode of the MFL device may include a split gate that is formed by a self-aligning method. An example of a method of forming the self-aligned split gate is disclosed in U.S. Pat. No. 4,553,316. According to the disclosed method, a control gate is formed to have the split gate shape. Thus, a coupling coefficient of a memory cell having under a minute design rule increases. The gate electrode having a high efficiency of elimination/program may also be formed.
In a method of forming a MFL device, a substrate is divided into a memory device region and a logic device region. An isolation process is performed against the substrate to divide the substrate into an active region and a field region. A first silicon oxide layer is formed on the substrate. A first polysilicon layer is formed on the first silicon oxide layer. A first nitride layer pattern is formed on the first polysilicon layer. The first polysilicon layer is partially etched using the first nitride layer pattern as an etching mask until the first polysilicon layer is exposed. A second silicon oxide layer is formed on the first nitride layer pattern and the exposed first polysilicon layer.
The second silicon oxide layer is anisotropically etched to form a second silicon oxide layer pattern on a sidewall of the first nitride layer pattern. The first polysilicon layer and the first silicon oxide layer are etched using the second silicon oxide layer pattern as an etching mask to expose a surface of the substrate. A third silicon oxide layer pattern is formed on a sidewall of the first polysilicon layer. Impurities are then implanted into the exposed surface of the substrate to form a source region. Polysilicon is deposited to fill a space between the second silicon oxide layer patterns to form a source line electrically connected to the substrate. The first nitride layer pattern is then removed. The first polysilicon layer and the first silicon oxide layer are subsequently etched to form a split gate structure. Here, the layers formed in the logic device region are entirely etched to expose the surface of the substrate.
A fourth silicon oxide layer is formed in the split gate structure. A second polysilicon layer is formed on the fourth silicon oxide layer. A second silicon nitride layer is formed on the second polysilicon layer. The second polysilicon layer and the second silicon nitride layer are planarized. The second silicon nitride layer is then removed. The substrate is thermally oxidized to selectively form a fifth silicon oxide layer on the source line and the second polysilicon layer. A photoresist pattern defining a gate electrode of a logic circuit is formed on the second polysilicon layer in the logic device region. The second polysilicon layer is anisotropically etched using the photoresist pattern as an etching mask to form a word line on a sidewall of the split gate structure and a gate pattern on the logic device region.
However, since the second polysilicon layer is etched to simultaneously form the word line and the gate pattern, sizes of the word line and the gate pattern may not be readily controlled. That is, when the gate pattern is too thin, a channel length of the word line is reduced. On the contrary, when the gate pattern is too thick, the channel length of the word line is augmented.
When a line width of the gate pattern is reduced due to the highly-integrated semiconductor device, the gate pattern having adequate thickness is required. Accordingly, the word line may have a short channel length which effects the controllability of its threshold voltage. Uncontrollability of the threshold voltage may result in failure of the semiconductor device (e.g. a punch-through). Further, as the channel length of the word line is reduced, the program/elimination of the semiconductor device may malfunction.